A memory device including a memory core which is slow relative to output drivers and input receivers may use parallel to serial conversion for read operations and serial to parallel conversion for write operations. For example, assuming single data rate processing with eight bit shift registers, an output read shift register can be loaded in parallel once every eight bit times, with the resulting data shifted out onto the data bus one bit at a time. Similarly, an input write shift register can accumulate eight bits of incoming data, which are then presented to the memory core simultaneously. The conversions are used to match the relatively slow speed of the memory core with the higher speeds of the output drivers and input receivers. If the device uses double data rate processing, which transmits data on both edges of the clock, additional circuitry may be included to relax the timing requirements by separating even and odd data bits during read and write operations.
Typically, the memory device will have a certain number of address and control pins, used to transfer control and address information, and a certain number of data pins, used to transfer data between the memory and an external bus. Each data pin communicates via input/output (I/O) circuitry with the portion of the memory associated with the data pin. For a single data rate system, the I/O circuitry includes an input write shift register, an output read shift register, an input receiver, an output driver, and the read/write data lines between the shift registers and the memory. Each pair of read/write data lines is associated with a sub-portion of the memory. In the example discussed above, there would be eight pairs of read/write data lines between the portion of the memory associated with the data pin and the shift registers for each data pin. If there are eight data pins, the device will include 64 pairs of read/write data lines.
There exist various prior art schemes for compensating for damaged memory cells by providing redundant columns within the memory core. Cells within these redundant columns are used in place of damaged memory cells in regular (non-redundant) columns. In a memory device using serial-to-parallel conversion for write operations, and parallel-to-serial conversion for read operations, there are a large number of read/write data lines connected to the memory core. The redundancy scheme must be able to ensure that the correct data will be shifted out onto the bus at the appropriate time.
One common redundancy scheme is to add one or more spare columns in each sub-portion corresponding to a pair of read/write data lines. When there is a damaged cell within one of the regular columns in that sub-portion, the read from the damaged cell is suppressed, and the data is written to or read from the spare column instead. A disadvantage of this approach is that the redundancy address match and suppressing the access to the damaged cell location may limit column access time. Additionally, the number of spare columns required is relatively large, because each spare column can be used only within the sub-portion corresponding to a particular pair of read/write data lines. Therefore, the memory device will require at least one spare column for each pair of read/write data lines, and that will be insufficient if there is more than one failure in a sub-portion.
Another common redundancy scheme is to provide one or more spare columns in the array associated with each data pin. A multiplexor is included for each read/write data line, to substitute a cell of the spare column for a damaged cell in one of the regular columns in the sub-portion associated with that read/write data line. Use of the redundant columns is more flexible in this scheme, since a redundant column may be used for any read/write data line associated with a particular data pin. However, the wiring and multiplexing required is fairly substantial. Furthermore, the relatively high capacitance of the spare lines, due to their length, makes them slow to operate, potentially limiting column access time.
Thus, there a need in the art for a column redundancy scheme which is flexible, relatively fast, and does not require significant wiring and multiplexing.